1. Field of the Invention
The present invention relates generally to hot carrier effects (HCEs) within metal oxide semiconductor field effect transistors (MOSFETs). More particularly, the present invention relates to methods for attenuating hot carrier effects (HCEs) within metal oxide semiconductor field effect transistors (MOSFETs).
2. Description of the Related Art
As integrated circuit integration levels have increased and integrated circuit device and conductor element dimensions have decreased, various novel effects have become more pronounced within advanced integrated circuit microelectronics fabrications. Within advanced integrated circuit microelectronics fabrications which have fabricated therein metal oxide semiconductor field effect transistors (MOSFETs), a particularly common and generally detrimental effect incident to forming those metal oxide semiconductor field effect transistors (MOSFETs) with decreased dimensions is the hot carrier effect (HCE).
The hot carrier effect (HCE) derives from injection of charge carriers into gate dielectric layers typically formed of silicon oxide formed beneath gate electrode edges within advanced metal oxide semiconductor field effect transistors (MOSFETs). The injection of the charge carriers results from decreased channel widths and decreased gate dielectric layer thicknesses within advanced metal oxide semiconductor field effect transistors (MOSFETs) while maintaining constant advanced metal oxide semiconductor field effect transistor (MOSFET) operating voltage. The decreased channel widths and decreased gate dielectric layer thicknesses within advanced metal oxide semiconductor field effect transistors (MOSFETs) at constant metal oxide semiconductor field effect transistor (MOSFET) operating voltage typically provide increased electrical field gradients at gate electrode edges within advanced metal oxide semiconductor field effect transistors (MOSFETs), through which increased electrical field gradients charge carriers are injected into gate dielectric layers.
Along with other characteristics, the hot carrier effect (HCE) within an advanced metal oxide semiconductor field effect transistor (MOSFET) is typically manifested as: (1) an increased sub-threshold current within the metal oxide semiconductor field effect transistor (MOSFET); and (2) a drift in threshold voltage within the metal oxide semiconductor field effect transistor (MOSFET). Hot carrier effect (HCE) damage sustained by a metal oxide semiconductor field effect transistor (MOSFET) is often cumulative and typically results in premature metal oxide semiconductor field effect transistor (MOSFET) failure. Since inhomogeneous electrical properties within metal oxide semiconductor field effect transistors (MOSFETs) and premature failure of metal oxide semiconductor field effect transistors (MOSFETs) are undesirable within advanced metal oxide semiconductor field effect transistor (MOSFET) operation, it is thus towards the goal of attenuating hot carrier effects (HCEs) within advanced metal oxide semiconductor field effect transistors (MOSFETs) that the present invention is generally directed.
Various methods have been disclosed in the art of integrated circuit microelectronics fabrication for controlling hot carrier effects (HCEs) within metal oxide semiconductor field effect transistors (MOSFETs). In addition, there has also been disclosed in the art of integrated circuit microelectronics fabrication various methods for forming contact layers upon source/drain electrodes within metal oxide semiconductor field effect transistors (MOSFETs) of line width dimensions which may be susceptible to hot carrier effects (HCEs).
For example, Haken et al., in U.S. Pat. No. 5,389,809 disclose a dual ion implant method for forming a pair of source/drain regions within a metal oxide semiconductor field effect transistors (MOSFET) to provide the metal oxide semiconductor field effect transistor (MOSFET) with enhanced hot carrier effect (HCE) resistance. The dual ion implant method employs two separate dopants of differing diffusivity within the pair of source/drain regions of the metal oxide semiconductor field effect transistor (MOSFET), such that upon thermal annealing of the metal oxide semiconductor field effect transistor (MOSFET) there is formed within the pair of source/drain regions dopant concentration gradients at the gate electrode edges.
In addition, Hsu, in U.S. Pat. No. 5,491,099 discloses a method for fabricating a silicided lightly doped drain (LDD) within a metal oxide semiconductor field effect transistor (MOSFET) to provide the metal oxide semiconductor field effect transistor (MOSFET) with enhanced hot carrier effect (HCE) resistance. The method recesses a lightly doped drain (LDD) low dose ion implant structure of the metal oxide semiconductor field effect transistor (MOSFET) within a semiconductor substrate within and upon which is formed the metal oxide semiconductor field effect transistor (MOSFET) to simultaneously form the metal oxide semiconductor field effect transistor (MOSFET) with enhanced hot carrier effect (HCE) resistance and decreased channel length.
Further, Inoue et al., in U.S. Pat. No. 5,413,968 discloses a method for forming within an integrated circuit microelectronics fabrication a metal silicide interconnect layer contacting a source/drain region of a metal oxide semiconductor field effect transistor (MOSFET) formed within and upon a semiconductor substrate within the integrated circuit microelectronics fabrication. The method employs a barrier layer formed upon the source/drain region and beneath a polysilicon layer which is subsequently completely consumed when forming the metal silicide interconnect layer through thermal annealing with a metal layer overlying the polysilicon layer. Through the method there is avoided consumption of silicon from the semiconductor substrate when thermally annealing the polysilicon layer and the metal layer to form the metal silicide interconnect layer.
Finally, Yen et al., in U.S. Pat. No. 5,510,296 discloses a method for forming within an integrated circuit microelectronics fabrication a tungsten silicide polycide contact layer contacting a source/drain region within a metal oxide semiconductor field effect transistor (MOSFET). The method employs an amorphous silicon underlayer formed upon the source/drain region and a chemical vapor deposited (CVD) tungsten silicide layer formed thereupon, where the tungsten silicide layer and the amorphous silicon underlayer are simultaneously annealed within a nitrogen containing atmosphere to form the tungsten silicide polycide contact layer contacting the source/drain region.
Desirable in the art of integrated circuit microelectronics fabrication are additional methods and materials through which there may be formed metal oxide semiconductor field effect transistors (MOSFETs) which have enhanced hot carrier (HCE) resistance. It is towards that goal that the present invention is directed.